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008    100324s1987    nyua    ob    001 0 eng d 
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042    dlr 
049    INap 
082 04 621.381/73 
082 04 621.381/73|219 
099    eBook O’Reilly for Public Libraries 
100 1  Bardell, Paul H. 
245 10 Built-in test for VLSI :|bpseudorandom techniques /|cPaul 
       H. Bardell, William H. McAnney, Jacob Savir.|h[O'Reilly 
       electronic resource] 
260    New York :|bWiley,|c©1987. 
300    1 online resource (xiii, 354 pages) :|billustrations 
336    text|btxt|2rdacontent 
337    computer|bc|2rdamedia 
338    online resource|bcr|2rdacarrier 
347    text file 
504    Includes bibliographical references (pages 339-345) and 
       index. 
505 0  Digital testing and the need for testable design -- 
       Principles of testable design -- Pseudorandom sequence 
       generators -- Test response compression techniques -- 
       Shift-register polynomial division -- Special-purpose 
       shift-register circuits -- Random pattern built-in test --
       Built-in test structures -- Limitations and other concerns
       of random pattern testing -- Test system requirements for 
       built-in test -- Appendix -- References -- Index. 
506    |3Use copy|fRestrictions unspecified|2star|5MiAaHDL 
520    This handbook provides ready access to all of the major 
       concepts, techniques, problems, and solutions in the 
       emerging field of pseudorandom pattern testing. Until now,
       the literature in this area has been widely scattered, and
       published work, written by professionals in several 
       disciplines, has treated notation and mathematics in ways 
       that vary from source to source. This book opens with a 
       clear description of the shortcomings of conventional 
       testing as applied to complex digital circuits, revewing 
       by comparison the principles of design for testability of 
       more advanced digital technology. Offers in-depth 
       discussions of test sequence generation and response data 
       compression, including pseudorandom sequence generators; 
       the mathematics of shift-register sequences and their 
       potential for built-in testing. Also details random and 
       memory testing and the problems of assessing the 
       efficiency of such tests, and the limitations and 
       practical concerns of built-in testing. 
533    Electronic reproduction.|b[Place of publication not 
       identified] :|cHathiTrust Digital Library,|d2010.|5MiAaHDL
538    Master and use copy. Digital master created according to 
       Benchmark for Faithful Digital Reproductions of Monographs
       and Serials, Version 1. Digital Library Federation, 
       December 2002.|uhttp://purl.oclc.org/DLF/benchrepro0212
       |5MiAaHDL 
542    |fCopyright © Wiley-Interscience|g1987 
546    English. 
583 1  digitized|c2010|hHathiTrust Digital Library|lcommitted to 
       preserve|2pda|5MiAaHDL 
588 0  Print version record. 
590    O'Reilly|bO'Reilly Online Learning: Academic/Public 
       Library Edition 
650  0 Integrated circuits|xVery large scale integration
       |xTesting. 
650  6 Circuits intégrés à très grande échelle|xEssais. 
650  7 Integrated circuits|xVery large scale integration|xTesting
       |2fast 
650  7 Electrical & Computer Engineering.|2hilcc 
650  7 Engineering & Applied Sciences.|2hilcc 
650  7 Electrical Engineering.|2hilcc 
653    Electronic equipment|aVery large scale integrated circuits
       |aTesting 
700 1  McAnney, William H. 
700 1  Savir, Jacob. 
776 08 |iPrint version:|aBardell, Paul H.|tBuilt-in test for 
       VLSI.|dNew York : Wiley, ©1987|w(DLC)   87023013
       |w(OCoLC)16580098 
856 40 |uhttps://ezproxy.naperville-lib.org/login?url=https://
       learning.oreilly.com/library/view/~/9780471624639/?ar
       |zAvailable on O'Reilly for Public Libraries 
994    92|bJFN