| Description |
1 online resource (xiii, 354 pages) : illustrations |
|
text file |
| Bibliography |
Includes bibliographical references (pages 339-345) and index. |
| Contents |
Digital testing and the need for testable design -- Principles of testable design -- Pseudorandom sequence generators -- Test response compression techniques -- Shift-register polynomial division -- Special-purpose shift-register circuits -- Random pattern built-in test -- Built-in test structures -- Limitations and other concerns of random pattern testing -- Test system requirements for built-in test -- Appendix -- References -- Index. |
| Access |
Use copy Restrictions unspecified star MiAaHDL |
| Reproduction |
Electronic reproduction. [Place of publication not identified] : HathiTrust Digital Library, 2010. MiAaHDL |
| System Details |
Master and use copy. Digital master created according to Benchmark for Faithful Digital Reproductions of Monographs and Serials, Version 1. Digital Library Federation, December 2002. http://purl.oclc.org/DLF/benchrepro0212 MiAaHDL |
| Processing Action |
digitized 2010 HathiTrust Digital Library committed to preserve pda MiAaHDL |
| Summary |
This handbook provides ready access to all of the major concepts, techniques, problems, and solutions in the emerging field of pseudorandom pattern testing. Until now, the literature in this area has been widely scattered, and published work, written by professionals in several disciplines, has treated notation and mathematics in ways that vary from source to source. This book opens with a clear description of the shortcomings of conventional testing as applied to complex digital circuits, revewing by comparison the principles of design for testability of more advanced digital technology. Offers in-depth discussions of test sequence generation and response data compression, including pseudorandom sequence generators; the mathematics of shift-register sequences and their potential for built-in testing. Also details random and memory testing and the problems of assessing the efficiency of such tests, and the limitations and practical concerns of built-in testing. |
| Language |
English. |
| Subject |
Integrated circuits -- Very large scale integration -- Testing.
|
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Circuits intégrés à très grande échelle -- Essais. |
|
Integrated circuits -- Very large scale integration -- Testing |
|
Electrical & Computer Engineering. |
|
Engineering & Applied Sciences. |
|
Electrical Engineering. |
| Indexed Term |
Electronic equipment Very large scale integrated circuits Testing |
| Added Author |
McAnney, William H.
|
|
Savir, Jacob.
|
| Other Form: |
Print version: Bardell, Paul H. Built-in test for VLSI. New York : Wiley, ©1987 (DLC) 87023013 (OCoLC)16580098 |
| Standard No. |
9780471624639 |
|
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